1. Field of Invention
This invention relates to semiconductor devices and more particular to electrostatic discharge devices with a guard ring structure to block high energy current from the internal circuits.
2. Description of the Related Art
An ESD (electrostatic discharge) device or circuit is used to protect internal circuitry on a semiconductor chip. The ESD devices and circuits are connected to each chip I/O (input/output) and power pad. When an electrostatic discharge external to the chip enters a chip pad, the ESD devices and circuits absorb the resulting high current and protect the internal chip circuitry form damage. The ESD circuits are comprised of diodes and bipolar and MOS devices, and the ESD devices or circuits are usually located near the chip pad to which they are connected.
In U.S. Pat. No. 5,912,494 (Yu) an ESD structure is described in which a heavily doped polycrystalline region is deposited on the surface of a semiconductor substrate. The polycrystalline region is used to create a lightly doped region to be formed which in turn increases the turn on voltage of a parasitic bipolar transistor. The parasitic transistor is prevented from turning on during an ESD event, allowing an ESD device to protect the internal circuits of the chip. In U.S. Pat. No. 5,438,005 (Jang) a CMOS device is provided with a deep collector guard ring which provide immunity to latch-up of the CMOS device. In U.S. Pat. No. 5,223,737 (Canclini) An ESD circuit is created with a deep N-well which forms a bipolar transistor with a resistor and zener diode to form ESD protection to internal circuits from electrostatic discharge entering a chip pad.
An ESD device or circuit is necessary for each chip bond pad to prevent damage or latch-up during an electrostatic discharge or applied voltage overshoot and voltage undershoot. When an electrostatic discharge enters a bond pad, the ESD device will attempt to absorb the resulting high current so that the internal circuits are not affected. Usually the ESD device or circuit is surrounded by either a N+, a P+, or both guard rings. These guard rings are used to prevent damage from voltage latch-up resulting from ESD and voltage overshooting or undershooting. Absorption of high current by the guard rings from an ESD or a voltage overshoot or undershoot helps prevent damage of the ESD device from overheating and resists current further flow to the internal circuits of the semiconductor chip. The effectiveness of the guard rings depend on the depth to which the guard rings are produced to block and absorb unwanted currents.